With the development of the IC manufacturing technology, the size of field effect transistor (FET) has been reducing. So, strain technology has been introduced to change lattice structure of channel for improving the carrier mobility in a channel. It has been known from the existing studies that the application of tensile stress in the channel can increase the electron mobility, while the application of compressive stress can increase the hole mobility.
Since the semiconductor manufacturing technology has been developed into the nano-scale, scaling down technology is facing more and more serious challenges. New technologies are needed to enhance the performance of the FET, of which strained silicon technology has been widely used, especially the application of embedded SiGe technology.
In the embedded SiGe technology, SiGe compound is embedded into the source region and the drain region to provide a compressive stress to the channel, so as to greatly improve the performance of the PMOS.
Referring to the FIGS. 1-4, a method of preparing SiGe source/drain in the prior art is described, which comprises the steps of:
Step S01: providing a semiconductor single crystal silicon substrate, and preparing a gate and a mask on the semiconductor single crystal silicon substrate (shown in the FIG. 1); wherein, the semiconductor single crystal silicon substrate can be a SOI substrate;
Step S02: patterning etching the semiconductor single crystal silicon substrate to form recesses (shown in the FIG. 2);
Step S03: epitaxially growing a SiGe seed layer and a SiGe bulk layer in the recesses of the semiconductor single crystal silicon substrate in turn;
Specifically, in the embedded SiGe technology, due to epitaxial growth has crystal orientation selectivity (such as, epitaxial growth is the fastest in the <100> crystal orientation, faster in the <110> crystal orientation, and almost impossible in the <111> crystal orientation), the <111> crystal plane of the SiGe epitaxy in the un-tuck structure more easily formed at the area near the STI structure will restrain the growth of the SiGe seed layer and the SiGe bulk layer, so cause the insufficient of thickness of the SiGe seed layer and the SiGe bulk layer, as shown in the FIG. 3.
Step S04: epitaxially growing a cap layer on top of the SiGe seed layer and the SiGe bulk layer.
Specifically, the formed <111> crystal plane at the Step S03 also restrains the growth of the cap layer, so the cap layer grown on the <111> crystal plane in the un-tuck structure becomes uneven as shown in the FIG. 4. In other words, the thickness of the cap layer grown on the <111> crystal plane is insufficient.
It is well known by the person skilled in the art that, in the subsequent metal silicide reaction, Ni atom is easy to infiltrate into the bottom semiconductor single crystal silicon substrate, so that lead to the leakage of the active area. In addition, SiGe epitaxy with high germanium concentration is difficult to react with Ni to form metal silicide (NiSi or NiGeSi), so that cause poor contact between subsequent contact hole and the SiGe epitaxy, and further cause leakage, increased resistance and uncontrolled resistance, and so on.